1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device such as an SRAM (Static Random Access Memory) which can be operated at a low power supply voltage.
2. Description of the Related Art
An SRAM is popularly used as a cache memory such as an ASIC (Application-Specific Integrated Circuit) used in a mobile terminal or the like. Since the SRAM used for such a purpose uses a battery having a limited capacity as a power supply, the SRAM must be small in size and must be operated at a low power consumption. Since a power consumption is in proportion to the square of a power supply voltage, a reduction in power supply voltage is most effective in reducing a power consumption.
On the other hand, the reduction in power supply voltage reduces the operation speeds of MOS transistors constituting the SRAM. For this reason, the operation speeds of the MOS transistors are increased by reducing the threshold voltages of the MOS transistors. However, when the threshold voltage is reduced, a leak current generated by a sub-threshold current increases in a standby state to make it difficult to achieve an effective reduction in power consumption.
In order to solve the above object, a CMOS (Complementary MOS transistor) LSI technique which can be operated at a low power consumption in an active state and which slightly increases a power consumed by a leak current in a standby state, an MTCMOS (Multi-Threshold CMOS) technique is known.
FIG. 4 is a diagram showing the configuration of a conventional SRAM to which an MTCMOS technique described in Reference xe2x80x9cTechnical Report of IEICE, ICD97-52 (1997-6), IEICE, Shibata, Morimura et al. xe2x80x9c1-V Operating 0.25 xcexcm SRAM Macro-cell for Mobile Devicexe2x80x9d pp. 1 to 8xe2x80x9d.
This SRAM has a flip-flop (FF) 20 constituted by two inverters L1 and L2 connected to storage nodes N11 and N12, respectively, and each having a high threshold voltage. The storage nodes N11 and N12 are connected to bit line pair BL and /BL through write transistors Q1 and Q2 driven by a selection signal X of a word line WL and having a high threshold voltage.
In addition, the SRAM has read acceleration transistors Q3 and Q4 driven by the selection signal X of the word line WL and each having a low threshold voltage. The drain of the transistor Q3 is connected to the bit line BL, and the source thereof is connected to a virtual ground line VGND through a transistor Q5 having a low threshold voltage. Similarly, the drain of the transistor Q4 is connected to the bit line /BL, and the source thereof is connected to the virtual ground line VGND through a transistor Q6 having a low threshold voltage. The gates of the transistors Q5 and Q6 are connected to the storage nodes N12 and N11, respectively.
The virtual ground line VGND is connected to a ground potential GND through a transistor Q7 having a high threshold voltage. NOR between a bit line selection signal Y and a read control signal RE is generated by a logical gate L3 having a low threshold voltage and given to the gate of the transistor Q7.
The operation will be described below.
In a data write state, the word line WL goes to level xe2x80x9cHxe2x80x9d, the transistors Q1 and Q2 are turned on, and data of the bit line pair BL and /BL are held in a flip-flop 1. At this time, since the transistor Q7 is in an OFF state, the virtual ground line VGND is in a floating state, no current flows in the transistors Q3 and Q4, and a write operation can be performed without hindrance.
In a data read state, the transistor Q7 is turned on by an output signal from the logical gate L3, and the virtual ground line VGND is connected to the ground potential GND (=level xe2x80x9cLxe2x80x9d). The word line WL goes to level xe2x80x9cHxe2x80x9d, the transistors Q1 to Q4 are turned on. At this time, since any one of the storage nodes N11 and N12 is set at level xe2x80x9cHxe2x80x9d, any one of the transistors Q5 and Q6 is turned on. In this manner, the bit line is driven by the inverters L1 and L2, and the bit line is driven by the low-threshold-voltage transistors Q3 to Q6 each having high current drive capability, so that the read operation can be performed at a high speed.
In a standby state, the transistor Q7 having a high threshold voltage is turned off, so that leak currents generated by sub-threshold currents of the transistors Q3 to Q6 each having a low threshold voltage can be interrupted. In this manner, a low power consumption in the standby state can be achieved.
However, a conventional SRAM has the following problem. The inverters L1 and L2 each having a high threshold voltage and the transistors Q1, Q2, and Q7 each having a high threshold voltage must be formed independently of the transistors Q3 to Q6 each having a low threshold voltage and the logical gate L3 each having a low threshold voltage. In general, a threshold voltage is set by controlling a dose of ion implantation into a silicon substrate. For this reason, a plurality of implantation masks corresponding the levels of the threshold voltages are used, ion implantation must be performed in a plurality of steps, and manufacturing steps are complicated. In a standby state, in order to interrupt leak currents generated by the sub-threshold currents of the transistors Q3 to Q6 each having a low threshold voltage, the virtual ground line VGND must be used to make the circuit configuration complex disadvantageously.
In order to solve the above problem, according to the present invention, there is provided a semiconductor memory device includes: first and second bit lines for inputting/outputting complementary data; first and second transistors for controlling connection between a first storage node and the first bit line and connection between a second storage node and the second bit line on the basis of a selection signal, respectively; a flip-flop for holding potentials of the first and second storage nodes to output the potentials; and the following acceleration circuit to perform a high-speed read operation at a low power supply voltage.
The acceleration circuit is constituted by third and fourth transistors, having channel regions connected to the second storage node, for controlling connection between the first bit line and a common potential on the basis of the potential of the second storage node in a selection state or a data read state, and fifth and sixth transistors, having channel regions connected to the first storage node, for controlling connection between the second bit line and the common potential on the basis of the potential of the first storage node in a selection state or a data read state.
According to the present invention, since the semiconductor memory device is constituted as described above, the following operation will be performed.
For example, when the first and second storage nodes are set at levels xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d, respectively, in a data read state, the threshold voltages of the fifth and sixth transistors having channel regions connected to the first storage node set at level xe2x80x9cHxe2x80x9d decrease, and current drive capabilities of the fifth and sixth transistors are improved. In addition, the fifth and sixth transistors are turned on by the potential of the first storage node, and the second bit line is connected to the common potential. For this reason, data set at level xe2x80x9cLxe2x80x9d is rapidly output to the second bit line.